Author: Not specified Language: vhdl
Description: Not specified Timestamp: 2013-06-02 12:06:49 +0000
View raw paste Reply

library IEEE;  
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_ARITH.ALL;  
use IEEE.STD_LOGIC_UNSIGNED.ALL;  

entity fifo is  
port (  clk : in std_logic;  
        read : in std_logic;   --enable read,'0' otan den xrisimopoieitai.  
        write : in std_logic;    --enable write,'0' otan den xrisimopoieitai.  
        data_out : out std_logic_vector(7 downto 0);    --output  
        data_in : in std_logic_vector (7 downto 0);     --input  
        empty : out std_logic;     --ginetai '1' otan i oura einai adeia  
        full : out std_logic     --ginetai '1' otan i oura einai gemati  
     );  
end fifo;  

architecture Behavioral of fifo is  
type memory_type is array (0 to 15) of std_logic_vector(7 downto 0);  
signal memory : memory_type :=(others => (others => '0')); -- mnimi ouras  
signal Ar,Aw : std_logic_vector(7 downto 0) :="00000000"; --read/write deiktes.  
begin  
  process(clk)  
  begin  
    if(clk'event and clk='1' and read ='1') then  
      data_out <= memory(conv_integer(Ar));  
    --  error <= '0';  
      Ar <= Ar + '1';      -- deixnei stin epomeni diey8ynsi.  
    end if;  
    if(clk'event and clk='1' and write ='1') then  
      memory(conv_integer(Aw)) <= data_in;  
      Aw <= Aw + '1';   --deixnei stin epomeni diey8ynsi.  
    end if;  
    if(Ar = "11111111") then      --reset ton pointer.  
      Ar <= "00000000";  
    end if;  
    if(Aw = "11111111") then        --elegxoume an i oura einai adeia i gemati
      full <='1';  
      Aw <= "00000000";  
    else  
      full <='0';  
    end if;  
    if(Aw = "00000000") then   --elegxoume an i oura einai adeia i gemati
      empty <='1';  
    else  
      empty <='0';  
    end if;  
  end process;  
end Behavioral;
 
View raw paste Reply