LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;

entity RAM is
  port (
    clk   : in  std_logic;
    CE      : in  std_logic;
    r_w: in std_logic;
    address : in  std_logic_vector(9 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(7 downto 0)
  );
end entity RAM;

architecture RTL of RAM is

   type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(data_in'range);
   signal ram : ram_type;
   signal read_address : std_logic_vector(address'range);

begin

  RAM_Process: process(clk) is

  begin
    if rising_edge(clk) then
      if CE = '1' and r_w='0' then
        ram(to_integer(unsigned(address))) <= data_in;
      end if;
    end if;
      if falling_edge(clk) then
     if CE = '1' and r_w='1' then
      read_address <= address;
    end if;
  end if;
  end process RAM_Process;

  data_out <= ram(to_integer(unsigned(read_address))) ;

end architecture RTL;