Author: Not specified Language: vhdl
Description: Not specified Timestamp: 2013-06-02 12:05:24 +0000
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  1. LIBRARY IEEE;
  2. USE IEEE.STD_LOGIC_1164.all;
  3. USE IEEE.NUMERIC_STD.all;
  4.  
  5. entity RAM is
  6.   port (
  7.     clk   : in  std_logic;
  8.     CE      : in  std_logic;
  9.     r_w: in std_logic;
  10.     address : in  std_logic_vector(9 downto 0);
  11.     data_in  : in  std_logic_vector(7 downto 0);
  12.     data_out : out std_logic_vector(7 downto 0)
  13.   );
  14. end entity RAM;
  15.  
  16. architecture RTL of RAM is
  17.  
  18.    type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(data_in'range);
  19.    signal ram : ram_type;
  20.    signal read_address : std_logic_vector(address'range);
  21.  
  22. begin
  23.  
  24.   RAM_Process: process(clk) is
  25.  
  26.   begin
  27.     if rising_edge(clk) then
  28.       if CE = '1' and r_w='0' then
  29.         ram(to_integer(unsigned(address))) <= data_in;
  30.       end if;
  31.     end if;
  32.       if falling_edge(clk) then
  33.      if CE = '1' and r_w='1' then
  34.       read_address <= address;
  35.     end if;
  36.   end if;
  37.   end process RAM_Process;
  38.  
  39.   data_out <= ram(to_integer(unsigned(read_address))) ;
  40.  
  41. end architecture RTL;
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